FIG. 1 is a diagram illustrating a prior art frequency synthesizer employing one phase locked loop. Referring to FIG. 1, the frequency synthesizer, i.e. a single phase locked loop has a reference frequency oscillator 11, a phase detector 12, a low pass filter 13, a voltage controlled oscillator 14 and a frequency divider 15.
A synthesized frequency Fout is N times the reference frequency Fref being outputted from the reference frequency oscillator 11. Accordingly, the synthesizer having the output frequency Fout that is integer times the reference frequency Fref is called an integer-N frequency synthesizer.
However, the prior art frequency synthesizer has various disadvantages. For example, a phase noise performance is degraded when a channel spacing is reduced. The channel spacing refers to a spacing between frequencies that may be obtained by using the frequency synthesizer. In case of the integer-N phase locked loop of FIG. 1, the output frequency Fout is integer times the reference frequency Fref. Thus, the output frequency Fout may be increased or decreased by a unit of the reference frequency Fref, and the channel spacing is same as the reference frequency Fref.
Therefore, the reference frequency Fref should be lowered in order to reduce the channel spacing, that is, to in order to obtain dense frequencies. However, for stability of the phase locked loop, it is preferable that a bandwidth of the phase locked loop is less than one tenth of the reference frequency Fref. Therefore, the reference frequency Fref should be reduced in order to reduce the channel spacing, but the bandwidth is also reduced when the reference frequency Fref is reduced. Moreover, the phase noise is increased as the bandwidth of the phase locked loop is decreased because of an effect of a phase noise of the voltage controlled oscillator 14.
For example, when the output frequency Fout is required to be varied by having the channel spacing of 100 KHz within a range between 2.0 GHz and 2.1 GHz, the reference frequency Fref should be 100 KHz, and N should be capable of being varied within a range between 20000 and 21000. In addition, it is preferable that the bandwidth of the phase locked loop is no more than 10 KHz.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.